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Additional Product Information

TAPP: Data Sheet

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Typical TAPP Applications

  • ASICs, DSP, ASSP
  • High-speed networks
  • Personal digital assistants
  • RF applications
  • Telecommunications

TAPP U.S. Patents

US Pat. 6,498,099
US Pat. 6,635,957
US Pat. 6,872,661
US Pat. 6,933,594
US Pat. 6,946,324
US Pat. 6,964,918
US Pat. 6,989,294
US Pat. 6,995,460
US Pat. 7,009,286
US Pat. 7,033,517
US Pat. 7,049,177
US Pat. 7,081,403
US Pat. 7,226,811
US Pat. 7,232,755
US Pat. 7,271,032

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TAPP®

Thin Array Plastic Package

LPCCA revolutionary new concept, ASAT's TAPP® is a leadless, Pb-free and multi-row packaging solution. The very thin, fine-pitch package with an exposed die attach pad allows for improved thermal performance and a power/ground ring option for enhanced electrical characteristics. The TAPP® offers a superior solution for high-performance and chip scale applications.

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Features

  • Body sizes from 2 to 10 mm SQ*
  • Lead counts from 8 to 72
  • Standard assembly materials, equipment and processes
  • Ground plane bonding option
  • Conforms to JEDEC registered outlines for QFN (MO-220) and SON (MO-229)
  • Dual-in-line versions available
  • 0.4 mm, 0.5 mm and 0.65 mm thickness options per JEDEC outline MO-248
  • Bumped LPCC available per JEDEC outline MO-250
  • Stacked die option available

Advantages

  • Moisture Sensitivity Level One (MSL-1) and “green” options available
  • Lowest stress at solder joint compared to CSP & Flex packages
  • Saw singulation technique provides larger die pads for better thermal performance
  • Very low inductance for high-speed applications
  • Ten day design cycle time including lead frame
  • Immune to die shrink
  • Die pad mounting to motherboard provides for excellent thermal performance

Typical Cross Section

TAPP